Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

Altera Corporation 5–3
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Device Family
Support
All Nios II cores provide the same support for target Altera device
families. Nios II cores provide either full or preliminary device family
support, as described below:
■ Full support means the Nios II cores meet all functional and timing
requirements for the device family and may be used in production
designs
■ Preliminary support means the Nios II cores meet all functional
requirements, but might still be undergoing timing analysis for the
device family; they may be used in production designs with caution.
Table 5–2 shows the level of support offered to each of the Altera device
families by the Nios II cores.
Nios II/f Core
The Nios II/f “fast” core is designed for high execution performance.
Performance is gained at the expense of core size. The base Nios II/f
coreis approximately 25% larger than the Nios II/s core. Altera designed
the Nios II/f core with the following design goals in mind:
■ Maximize the instructions-per-cycle execution efficiency
■ Maximize f
MAX
performance of the processor core
The resulting core is optimal for performance-critical applications, as well
as for applications with large amounts of code and/or data, such as
systems running a full-featured operating system.
Table 5–2. Device Family Support
Device Family Support
Arria
™
GX
Full
Stratix
®
III
Preliminary
Stratix
II
Full
Stratix II GX Full
Stratix GX Full
Stratix Full
Hardcopy
®
II Full
HardCopy Full
Cyclone
®
III
Full
Cyclone II Full
Cyclone Full
Other device families No support