Specifications

5–2 Altera Corporation
Nios II Processor Reference Handbook October 2007
Introduction
Instruction
Bus
Cache – 512 bytes to
64 KBytes
512 bytes to 64 KBytes
Pipelined Memory Access – Yes Yes
Branch Prediction – Static Dynamic
Tightly-Coupled Memory – Optional Optional
Data Bus Cache – – 512 bytes to 64 KBytes
Pipelined Memory Access – – –
Cache Bypass Methods – – I/O instructions; bit-31
cache bypass
Tightly-Coupled Memory – – Optional
Arithmetic
Logic Unit
Hardware Multiply – 3-Cycle (3) 1-Cycle (3)
Hardware Divide – Optional Optional
Shifter 1 Cycle-per-bit 3-Cycle Shift (3) 1-Cycle Barrel
Shifter (3)
JTAG
Debug
Module
JTAG interface, run
control, software
breakpoints
Optional Optional Optional
Hardware Breakpoints – Optional Optional
Off-Chip Trace Buffer – Optional Optional
Exception
Handling
Exception Types Software trap,
unimplemented
instruction,
hardware interrupt
Software trap,
unimplemented
instruction,
hardware interrupt
Software trap,
unimplemented
instruction,
hardware interrupt
Integrated Interrupt
Controller
Ye s Ye s Ye s
User Mode Support No; Permanently in
supervisor mode
No; Permanently in
supervisor mode
No; Permanently in
supervisor mode
Custom Instruction Support Yes Yes Yes
Notes to Ta b le 5 – 1 :
(1) DMIPS performance for the Nios II/s and Nios II/f cores depends on the hardware multiply option.
(2) Using the fastest hardware multiply option, and targeting a Stratix II FPGA in the fastest speed grade.
(3) Multiply and shift performance depends on which hardware multiply option is used. If no hardware multiply
option is used, multiply operations are emulated in software, and shift operations require one cycle per bit. For
details, see the arithmetic logic unit description for each core.
Table 5–1. Nios II Processor Cores (Part 2 of 2)
Feature Core
Nios II/e Nios II/s Nios II/f