Specifications

Altera Corporation 5–1
October 2007
5. Nios II Core
Implementation Details
Introduction
This document describes all of the Nios
®
II processor core
implementations available at the time of publishing. This document
describes only implementation-specific features of each processor core.
All cores support the Nios II instruction set architecture.
f For more information regarding the Nios II instruction set architecture,
refer to the Instruction Set Reference chapter of the Nios II Processor
Reference Handbook.
For common core information and details on a specific core, see the
appropriate section:
■ “Device Family Support” on page 5–3
■ “Nios II/f Core” on page 5–3
■ “Nios II/s Core” on page 5–12
■ “Nios II/e Core” on page 5–19
Table 5–1 compares the objectives and features of each Nios II processor
core. The table is designed to help system designers choose the core that
best suits their target application.
Table 5–1. Nios II Processor Cores (Part 1 of 2)
Feature Core
Nios II/e Nios II/s Nios II/f
Objective Minimal core size Small core size Fast execution speed
Performance DMIPS/MHz (1) 0.15 0.74 1.16
Max. DMIPS (2) 31 127 218
Max. f
MAX
(2) 200 MHz 165 MHz 185 MHz
Area < 700 LEs;
< 350 ALMs
< 1400 LEs;
< 700 ALMs
< 1800 LEs;
< 900 ALMs
Pipeline 1 Stage 5 Stages 6 Stages
External Address Space 2 GBytes 2 GBytes 2 GBytes
NII51015-7.2.0