Specifications

4–16 Altera Corporation
Nios II Processor Reference Handbook October 2007
Custom Instructions Page
1 To display custom instructions in the table of active components
on the SOPC Builder System Contents tab, click Filter in the
lower-right of the System Contents tab, and turn on Nios
Custom Instruction.
To create your own custom instruction using the component editor, click
Import. After finishing in the component editor, click Refresh
Component List on the File menu to add the new instruction to the list at
the left side of the Custom Instructions page.
f A complete discussion of the hardware and software design process for
custom instructions is beyond the scope of this chapter. For full details
on the topic of custom instructions, including working example designs,
see the Nios II Custom Instruction User Guide.
The following sections describe the default custom instructions Altera
provides.
Interrupt Vector Custom Instruction
The Nios II processor offers an interrupt vector custom instruction which
reduces average and worst case interrupt latency.
To add the interrupt vector custom instruction to the Nios II processor,
select Interrupt Vector from the list, and click Add.
There can only be one interrupt vector custom instruction component in
a Nios II processor. If the interrupt vector custom instruction is present in
the Nios II processor, the hardware abstraction layer (HAL) source
detects it at compile time and generates code using the custom
instruction.
The interrupt vector custom instruction improves both average and worst
case interrupt latency by up to 20%. To achieve the lowest possible
interrupt latency, consider using tightly-coupled memories so that
interrupt handlers can run without cache misses.
f For details of the interrupt vector custom instruction implementation,
see the Exception and Interrupt Controller section in the Processor
Architecture chapter of the Nios II Processor Reference Handbook. For
guidance with tightly-coupled memories, see the Tightly-Coupled Memory
section in the Processor Architecture chapter of the Nios II Processor
Reference Handbook.