Specifications

4–14 Altera Corporation
Nios II Processor Reference Handbook October 2007
Custom Instructions Page
Advanced Debug Settings
Debug levels 3 and 4 support trace data collection into an on-chip
memory buffer. You can set the on-chip trace buffer size to sizes from 128
to 64K trace frames, using OCI Onchip Trace. Larger buffer sizes
consume more on-chip M4K RAM blocks. Every M4K RAM block can
store up to 128 trace frames.
Debug level 4 also supports manual 2X clock signal specification. If you
want to use a specific 2X clock signal of your FPGA design, turn off
Automatically generate internal 2X clock signal and drive a 2X clock
signal into your SOPC Builder system manually.
f For further details on trace frames, refer to the Processor Architecture
chapter of the Nios II Processor Reference Handbook.
Custom
Instructions
Page
The Custom Instructions page allows you to connect custom instruction
logic to the Nios II arithmetic logic unit (ALU). You can achieve
significant performance improvements, often on the order of 10x to 100x,