Specifications

Altera Corporation 4–13
October 2007 Nios II Processor Reference Handbook
Instantiating the Nios II Processor in SOPC Builder
Table 4–2 on page 4–13 is a detailed list of the characteristics of each
debug level. Different levels consume different amounts of on-chip
resources. Certain Nios II cores have restricted debug options, and certain
options require debug tools provided by First Silicon Solutions (FS2) or
Lauterbach.
f For details on the debug features available from FS2, visit www.fs2.com,
and from Lauterbach, see www.lauterbach.com.
Break Vector
If the Nios II processor contains a JTAG debug module, SOPC Builder
determines a break vector (break location). Memory is always the
processor core you are configuring. Offset is fixed at 0x20. SOPC Builder
calculates the physical address of the break vector from the memory
module’s base address and the offset.
Table 4–2. JTAG Debug Module Levels
Debug Feature
No
Debug
Level 1 Level 2 Level 3 Level 4 (1)
Logic Usage 0 300 - 400 LEs 800 - 900 LEs 2,400 - 2,700 LEs 3,100 - 3,700 LEs
On-Chip Memory Usage 0 Two M4Ks Two M4Ks Four M4Ks Four M4Ks
External I/O Pins Required
(2)
00 0 0 20
JTAG Target Connection No Yes Yes Yes Yes
Download Software No Yes Yes Yes Yes
Software Breakpoints None Unlimited Unlimited Unlimited Unlimited
Hardware Execution
Breakpoints
0 None 2 2 4
Data Triggers 0 None 2 2 4
On-Chip Trace 0 None None Up to 64K Frames
(3)
Up to 64K Frames
Off-Chip Trace (4)
0 None None None 128K Frames
Notes to Ta b le 4 – 2 :
(1) Level 4 requires the purchase of a software upgrade from FS2 or Lauterbach.
(2) Not including the dedicated JTAG pins on the Altera FPGA.
(3) An additional license from FS2 is required to use more than 16 frames.
(4) Off-chip trace requires the purchase of additional hardware from FS2 or Lauterbach.