Specifications

Altera Corporation 4–11
October 2007 Nios II Processor Reference Handbook
Instantiating the Nios II Processor in SOPC Builder
Table 4–1 describes the debug features available to you for debugging
your system.
Table 4–1. Debug Configuration Features
Feature Description
JTAG Target
Connection
Connects to the processor through the standard JTAG pins on the Altera FPGA. This
provides the basic capabilities to start and stop the processor, and examine/edit
registers and memory.
Download Software Downloads executable code to the processor’s memory via the JTAG connection.
Software Breakpoints Sets a breakpoint on instructions residing in RAM
Hardware Breakpoints Sets a breakpoint on instructions residing in nonvolatile memory, such as flash
memory.
Data Triggers Triggers based on address value, data value, or read or write cycle. You can use a
trigger to halt the processor on specific events or conditions, or to activate other events,
such as starting execution trace, or sending a trigger signal to an external logic
analyzer. Two data triggers can be combined to form a trigger that activates on a range
of data or addresses.
Instruction Trace Captures the sequence of instructions executing on the processor in real time.
Data Trace Captures the addresses and data associated with read and write operations executed
by the processor in real time.
On-Chip Trace Stores trace data in on-chip memory.
Off-Chip Trace Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside
the Nios II core. Off-chip trace requires a debug probe from First Silicon Solutions (FS2)
or Lauterbach.