Specifications

4–10 Altera Corporation
Nios II Processor Reference Handbook October 2007
JTAG Debug Module Page
Reset Signals
Include cpu_resetrequest and cpu_resettaken signals adds processor-
only reset request signals to the Nios II processor. These signals let
another device individually reset the Nios II processor without resetting
the entire SOPC Builder system. The signals are exported to the top level
of your SOPC Builder system.
f For further details on the processor-only reset request signals, refer to the
Processor Architecture chapter of the Nios II Processor Reference Handbook.
JTAG Debug
Module Page
The JTAG Debug Module page presents settings for configuring the
JTAG debug module on the Nios II processor. You can select the debug
features appropriate for your target application.
Soft-core processors such as the Nios II processor offer unique debug
capabilities beyond the features of traditional-fixed processors. The soft-
core nature of the Nios II processor allows you to debug a system in
development using a full-featured debug core, and later remove the
debug features to conserve logic resources. For the release version of a
product, you might choose to reduce the JTAG debug module
functionality, or remove it altogether.