Specifications

4–8 Altera Corporation
Nios II Processor Reference Handbook October 2007
Caches and Memory Interfaces Page
Data Master Settings
The Data Master settings provide the following options for the Nios II/f
core:
■ Data Cache - Specifies the size of the data cache. Valid sizes are from
512 bytes to 64 KBytes, or None. Depending on the value specified
for Data Cache, the following options are available:
● Data Cache Line Size - Valid sizes are 4, 16, or 32 bytes.
● Omit data master port - If you set Data Cache to None, you can
optionally turn on Omit data master port to remove the
Avalon-MM data master port from the Nios II processor. In this
case, you must include a tightly-coupled data memory.
1 Although the Nios II processor can operate entirely out of
tightly-coupled memory without the need for Avalon-MM
instruction or data masters, software debug is not possible
when either the Avalon-MM instruction or data master is
omitted.
Enable Bursts - The Nios II processor can fill its data cache lines
using burst transfers. Usually you enable bursts on the processor's
data bus when processor data is stored in DRAM, and disable bursts
when processor data is stored in SRAM.
Bursting to DRAM typically improves memory bandwidth but
might consume additional FPGA resources. Be aware that when
bursts are enabled, accesses to slaves might go through additional
hardware (called "burst adapters") which might decrease f
MAX
.
Bursting is only enabled for data line sizes greater than 4 bytes. The
burst length is 4 for a 16 byte line size and 8 for a 32 byte line size.
Data cache bursts are always aligned on the cache line boundary. For
example, with a 32-byte Nios II data cache line, a cache miss to the
address 8 results in a burst with the following address sequence: 0, 4,
8, 12, 16, 20, 24 and 28.
■ Include tightly coupled data master port(s) - When turned on, the
Nios II processor includes tightly-coupled memory ports. You can
specify one to four ports with the Number of ports setting. Tightly-
coupled memory ports appear on the connection panel of the Nios II
processor in the SOPC Builder System Contents tab. You must
connect each port to exactly one memory component in the system.