Specifications

4–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
Caches and Memory Interfaces Page
Caches and
Memory
Interfaces Page
The Caches and Memory Interfaces page allows you to configure the
cache and tightly-coupled memory usage for the instruction and data
master ports. Figure 4–2 shows an example of the Caches and Memory
Interfaces page.
Figure 4–2. Caches and Memory Interfaces Page in the Nios II Processor MegaWizard