Specifications

4–4 Altera Corporation
Nios II Processor Reference Handbook October 2007
Core Nios II Page
■ None - This option conserves logic resources by eliminating multiply
hardware. Multiply operations are implemented in software.
Turning on Hardware Divide includes LE-based divide hardware in the
ALU. The Hardware Divide option achieves much greater performance
than software emulation of divide operations.
f For details on the performance effects of the Hardware Multiply and
Hardware Divide options, see the Nios II Core Implementation Details
chapter of the Nios II Processor Reference Handbook.
Reset Vector
You can select the memory module where the reset code (boot loader)
resides, and the location of the reset vector (reset address). The reset
vector cannot be configured until your system memory components are
in place.
The Memory list, which includes all memory modules mastered by the
Nios II processor, allows you to select the reset vector memory module.
In a typical system, you select a nonvolatile memory module for the reset
code.
Offset allows you to specify the location of the reset vector relative to the
memory module’s base address. SOPC Builder calculates the physical
address of the reset vector when you modify the memory module, the
offset, or the memory module’s base address, and displays the address
next to the Offset box.
f For details on reset exceptions, see the Programming Model chapter of
the Nios II Processor Reference Handbook.
Exception Vector
You can select the memory module where the exception vector (exception
address) resides, and the location of the exception vector. The exception
vector cannot be configured until your system memory components are
in place.
The Memory list, which includes all memory modules mastered by the
Nios II processor, allows you to select the exception vector memory
module. In a typical system, you select a low-latency memory module for
the exception code.