Specifications

Altera Corporation 4–3
October 2007 Nios II Processor Reference Handbook
Instantiating the Nios II Processor in SOPC Builder
The following sections describe the configuration settings available.
Core Selection
The main purpose of the Core Nios II page is to select the processor core.
The core you select on this page affects other options available on this and
other pages.
Currently, Altera
®
offers three Nios II cores:
■ Nios II/f—The Nios II/f “fast” core is designed for fast performance.
As a result, this core presents the most configuration options
allowing you to fine-tune the processor for performance.
■ Nios II/s—The Nios II/s “standard” core is designed for small size
while maintaining performance.
■ Nios II/e—The Nios II/e “economy” core is designed to achieve the
smallest possible core size. As a result, this core has a limited feature
set, and many settings are not available when the Nios II/e core is
selected.
As shown in Figure 4–1, the Core Nios II page displays a “selector guide”
table that lists the basic properties of each core.
f For complete details of each core, see the Nios II Core Implementation
Details chapter of the Nios II Processor Reference Handbook.
Multiply and Divide Settings
The Nios II/s and Nios II/f cores offer hardware multiply and divide
options. You can choose the best option to balance embedded multiplier
usage, logic element (LE) usage, and performance.
The Hardware Multiply setting for each core provides a subset of the
options in the following list:
■ DSP Block - Include DSP block multipliers in the arithmetic logic
unit (ALU). This option is only present when targeting devices that
have DSP block multipliers.
■ Embedded Multipliers - Include embedded multipliers in the ALU.
This option is only present when targeting devices that have
embedded multipliers.
■ Logic Elements - Include LE-based multipliers in the ALU. This
option achieves high multiply performance without consuming
embedded multiplier resources.