Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History
3–22 Altera Corporation
Nios II Processor Reference Handbook October 2007
Document Revision History
■ Application Binary Interface chapter of the Nios II Processor Reference
Handbook
■ Nios II Core Implementation Details chapter of the Nios II Processor
Reference Handbook
■ Exception Handling chapter of the Nios II Software Developer’s
Handbook
■ Cache and Tightly Coupled Memory chapter of the Nios II Software
Developer’s Handbook
■ Processor Architecture chapter of the Nios II Processor Reference
Handbook
■ Nios II Custom Instruction User Guide
Document
Revision History
Table 3–14 shows the revision history for this document.
Table 3–14. Document Revision History
Date & Document
Version
Changes Made Summary of Changes
October 2007
v7.2.0
● Reworked text to refer to break and reset as exceptions.
● Grouped exceptions, break, reset, and interrupts all under
Exception Processing.
● Added table showing all Nios II exceptions (by priority).
● Removed “ctl” references to control registers.
● Added jmpi instruction to tables.
May 2007
v7.1.0
● Added table of contents to Introduction section.
● Added Referenced Documents section.
March 2007
v7.0.0
No change from previous release.
November 2006
v6.1.0
No change from previous release.
May 2006
v6.0.0
No change from previous release.
October 2005
v5.1.0
No change from previous release.
May 2005
v5.0.0
No change from previous release.
September 2004
v1.1
● Added details for new control register ctl5.
● Updated details of debug mode and break processing to
reflect new behavior of the
break instruction.
May 2004
v1.0
Initial release.