Specifications

3–20 Altera Corporation
Nios II Processor Reference Handbook October 2007
Instruction Set Categories
The conditional-branch instructions do not have delay slots.
Other Control Instructions
Table 3–13 shows other control instructions.
Table 3–12. Conditional-Branch Instructions
Instruction Description
bge
bgeu
bgt
bgtu
ble
bleu
blt
bltu
beq
bne
These instructions provide relative branches that compare
two register values and branch if the expression is true.
See “Comparison Instructions” on page 3–17 for a
description of the relational operations implemented.
Table 3–13. Other Control Instructions
Instruction Description
trap
eret
The trap and eret instructions generate and return from exceptions. These instructions are
similar to the
call/ret pair, but are used for exceptions. trap saves the status register in
the
estatus register, saves the return address in the ea register, and then transfers execution
to the general exception handler.
eret returns from exception processing by restoring status
from
estatus, and executing the instruction specified by the address in ea.
break
bret
The break and bret instructions generate and return from breaks. break and bret are used
exclusively by software debugging tools. Programmers never use these instructions in
application code.
rdctl
wrctl
These instructions read and write control registers, such as the status register. The value is
read from or stored to a general-purpose register.
flushd
flushi
initd
initi
These instructions are used to manage the data and instruction cache memories.
flushp
This instruction flushes all pre-fetched instructions from the pipeline. This is necessary before
jumping to recently-modified instruction memory.
sync
This instruction ensures that all previously-issued operations have completed before allowing
execution of subsequent load and store operations.