Specifications

3–16 Altera Corporation
Nios II Processor Reference Handbook October 2007
Instruction Set Categories
The data transfer instructions in Table 3–6 support byte and half-word
transfers.
Arithmetic and Logical Instructions
Logical instructions support and, or, xor, and nor operations.
Arithmetic instructions support addition, subtraction, multiplication,
and division operations. See Table 3–7.
Table 3–6. Narrow Data Transfer Instructions
Instruction Description
ldb
ldbu
stb
ldh
ldhu
sth
ldb
, ldbu, ldh and ldhu load a byte or half-word from memory to a register. ldb and ldh sign-
extend the value to 32 bits, and
ldbu and ldhu zero-extend the value to 32 bits.
stb and sth store byte and half-word values, respectively.
Memory accesses can be cached or buffered to improve performance. To transfer data to I/O
peripherals, use the “io” versions of the instructions, described below.
ldbio
ldbuio
stbio
ldhio
ldhuio
sthio
These operations load/store byte and half-word data from/to peripherals without caching or
buffering.
Table 3–7. Arithmetic and Logical Instructions
Instruction Description
and
or
xor
nor
These are the standard 32-bit logical operations. These operations take two register values and
combine them bit-wise to form a result for a third register.
andi
ori
xori
These operations are immediate versions of the and, or, and xor instructions. The 16-bit
immediate value is zero-extended to 32 bits, and then combined with a register value to form the
result.
andhi
orhi
xorhi
In these versions of and, or, and xor, the 16-bit immediate value is shifted logically left by 16
bits to form a 32-bit operand. Zeroes are shifted in from the right.
add
sub
mul
div
divu
These are the standard 32-bit arithmetic operations. These operations take two registers as input
and store the result in a third register.