Specifications

Altera Corporation 3–15
October 2007 Nios II Processor Reference Handbook
Programming Model
Code written for a processor core with cache memory behaves correctly
on a processor core without cache memory. The reverse is not true.
Therefore, for a program to work properly on all Nios II processor core
implementations, the program must behave as if the instruction and data
caches exist. In systems without cache memory, the cache management
instructions perform no operation, and their effects are benign.
f For a complete discussion of cache management, see the Cache and
Tightly Coupled Memory chapter of the Nios II Software Developer’s
Handbook.
Some consideration is necessary to ensure cache coherency after
processor reset. See “Reset Exceptions” on page 3–6 for details.
f For details on the cache architecture and the memory hierarchy see the
Processor Architecture chapter of the Nios II Processor Reference Handbook.
Instruction Set
Categories
This section introduces the Nios II instructions categorized by type of
operation performed.
Data Transfer Instructions
The Nios II architecture is a load-store architecture. Load and store
instructions handle all data movement between registers, memory, and
peripherals. Memories and peripherals share a common address space.
Some Nios II processor cores use memory caching and/or write buffering
to improve memory bandwidth. The architecture provides instructions
for both cached and uncached accesses.
Table 3–5 describes the wide (32-bit) load and store instructions.
Table 3–5. Wide Data Transfer Instructions
Instruction Description
ldw
stw
The ldw and stw instructions load and store 32-bit data words from/to memory. The effective
address is the sum of a register's contents and a signed immediate value contained in the
instruction. Memory transfers can be cached or buffered to improve program performance. This
caching and buffering might cause memory cycles to occur out of order, and caching might
suppress some cycles entirely.
Data transfers for I/O peripherals should use
ldwio and stwio.
ldwio
stwio
ldwio and stwio instructions load and store 32-bit data words from/to peripherals without
caching and buffering. Access cycles for
ldwio and stwio instructions are guaranteed to occur
in instruction order and are never suppressed.