Specifications

3–14 Altera Corporation
Nios II Processor Reference Handbook October 2007
Memory and Peripheral Access
On the other hand, hardware interrupt exceptions must resume execution
from the interrupted instruction itself. In this case, the exception handler
must subtract 4 from ea to point to the interrupted instruction.
Memory and
Peripheral
Access
Nios II addresses are 32 bits, allowing access up to a 4 gigabyte address
space. However, many Nios II core implementations restrict addresses to
31 bits or fewer.
f For details, refer to the Nios II Core Implementation Details chapter of the
Nios II Processor Reference Handbook.
Peripherals, data memory, and program memory are mapped into the
same address space. The locations of memory and peripherals within the
address space are determined at system generation time. Reading or
writing to an address that does not map to a memory or peripheral
produces an undefined result.
The processor’s data bus is 32 bits wide. Instructions are available to read
and write byte, half-word (16-bit), or word (32-bit) data.
The Nios II architecture is little endian. For data wider than 8-bits stored
in memory, the more-significant bits are located in higher addresses.
The Nios II architecture supports register+immediate addressing.
Cache Memory
The Nios II architecture and instruction set accommodate the presence of
data cache and instruction cache memories. Cache management is
implemented in software by using cache management instructions.
Instructions are provided to initialize the cache, flush the caches
whenever necessary, and to bypass the data cache to properly access
memory-mapped peripherals.
The Nios II architecture provides a mechanism called bit-31 cache bypass
to bypass the cache depending on the value of the most-significant bit of
the address. The address space of processor cores that implement bit-31
cache bypass is 2 GBytes, and the high bit of the address controls the
caching of data memory accesses.
f Refer to the Nios II Core Implementation Details chapter of the Nios II
Processor Reference Handbook for details of which processor cores
implement bit-31 cache bypass.