Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

Altera Corporation 3–13
October 2007 Nios II Processor Reference Handbook
Programming Model
access to the code memory to read this address). If the instruction is trap,
the exception is a software trap. If the instruction at address ea-4 is one
of the instructions that can be implemented in software, the exception
was caused by an unimplemented instruction. See “Potential
Unimplemented Instructions” on page 3–21 for details. If none of the
above conditions apply, the exception type is unrecognized, and the
exception handler should report the condition.
Nested Exception Precautions
Exception routines must take special precautions before:
■ Issuing a trap instruction
■ Issuing an unimplemented instruction
■ Re-enabling hardware interrupts
Before allowing any of these actions, the exception routine must save
estatus and ea (r29), then restore them properly before returning to
preserve the pre-exception state of the exception registers.
Returning From Interrupt and Instruction-Related Exceptions
The eret instruction is used to resume execution at the pre-exception
address. Except for the et register (r24), the exception routine must
restore any registers modified during exception processing before
returning.
When executing the eret instruction, the processor:
1. Copies the contents of estatus to status
2. Transfers program execution to the address in the ea register (r29)
Return Address Considerations
The return address requires some consideration when returning from
exception processing routines. After an exception occurs, ea contains the
address of the instruction after the point where the exception occurred.
When returning from instruction-related exceptions, execution must
resume from the instruction following the instruction where the
exception occurred. Therefore, ea contains the correct return address.