Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

3–10 Altera Corporation
Nios II Processor Reference Handbook October 2007
Exception Processing
Instruction-Related Exceptions
Instruction-related exceptions occur during execution of Nios II
instructions and perform the steps outlined in “Processing Interrupt and
Instruction-Related Exceptions” on page 3–11.
The Nios II processor generates the following instruction-related
exceptions. All instruction-related exceptions are precise.
■ Trap instruction
■ Break instruction
■ Unimplemented instruction
Trap Instruction
When a program issues the trap instruction, it generates a software trap
exception. A program typically issues a software trap when the program
requires servicing by the operating system. The general exception
handler for the operating system determines the reason for the trap and
responds appropriately.
Break Instruction
The break instruction is treated as a break exception. Refer to “Break
Exceptions” on page 3–7 for details.
Unimplemented Instruction
When the processor issues a valid instruction that is not
implemented in hardware, an unimplemented instruction
exception is generated. The general exception handler
determines which instruction generated the exception. If the
instruction is not implemented in hardware, control is passed to
an exception routine that might choose to emulate the
instruction in software. See “Potential Unimplemented Instructions” on
page 3–21 for more information.
1 “Unimplemented instruction” does not mean “illegal
instruction.” Processor behavior for illegal instruction words is
dependent on the Nios II core. For most Nios II core
implementations, executing an illegal instruction produces an
undefined result. See the Nios II Core Implementation Details
chapter of the Nios II Processor Reference Handbook for details.