Specifications

Altera Corporation 3–9
October 2007 Nios II Processor Reference Handbook
Programming Model
Figure 3–1. Relationship Between ienable, ipending, PIE and Hardware
Interrupts
A software exception routine determines which of the pending interrupts
has the highest priority, and then transfers control to the appropriate
interrupt service routine (ISR). The ISR stops the interrupt from being
visible (either by clearing it at the source or masking it using ienable)
before returning and/or before re-enabling PIE. The ISR also saves
estatus and ea (r29) before re-enabling PIE.
Interrupts can be re-enabled by writing one to the PIE bit, thereby
allowing the current ISR to be interrupted. Typically, the exception
routine adjusts ienable so that IRQs of equal or lower priority are
disabled before re-enabling interrupts. See “Nested Exception
Precautions” on page 3–13 for more information.
IPENDING0
IPENDING1 IPENDING2
ipending Register
IPENDING31
irq0 irq1
irq2
irq31
31 0
IENABLE0
IENABLE1
IENABLE2
31 0
ienable Register
External hardware
interrupt request
inputs irq[31..0]
Relationship Between ienable, ipending, PIE, and
Interrupt Generation
. . .
. . .
. . .
PIE bit
Generate
Hardware
Interrupt
IENABLE31