Specifications

3–8 Altera Corporation
Nios II Processor Reference Handbook October 2007
Exception Processing
3. Writes the address of the instruction following the break to the ba
register (r30)
4. Transfers execution to the break handler, stored at the break vector
specified at system generation time
Register Usage
The bstatus control register and general-purpose registers bt (r25)
and ba (r30) are reserved for debugging. Code is not prevented from
writing to these registers, but debug code might overwrite the values. The
break handler can use bt (r25) to help save additional registers.
Returning From a Break
After processing a break, the break handler releases control of the
processor by executing a bret instruction. The bret instruction restores
status by copying the contents of bstatus and returns program
execution to the address in the ba register (r30). Aside from bt, all
registers are guaranteed to be returned to their pre-break state after
returning from the break handler.
Interrupt Exceptions
An external source such as a peripheral device can request a hardware
interrupt by asserting one of the processor’s 32 interrupt-request inputs,
irq0 through irq31. A hardware interrupt is generated if and only if all
three of these conditions are true:
■ The PIE bit of the status control register is one
■ An interrupt-request input, irqn, is asserted
■ The corresponding bit n of the ienable control register is one.
Upon hardware interrupt, the processor sets the PIE bit to zero, disabling
further interrupts, and performs the other steps outlined in “Processing
Interrupt and Instruction-Related Exceptions” on page 3–11.
The value of the ipending control register shows which interrupt
requests (IRQ) are pending. By peripheral design, an IRQ bit is
guaranteed to remain asserted until the processor explicitly responds to
the peripheral. Figure 3–1 shows the relationship between ipending,
ienable, PIE, and the generation of an interrupt.