Specifications

Altera Corporation 3–7
October 2007 Nios II Processor Reference Handbook
Programming Model
The reset state is undefined for all other system components, including
but not limited to:
■ General-purpose registers, except for zero (r0) which is
permanently zero.
■ Control registers, except for status which is reset to 0x0.
■ Instruction and data memory.
■ Cache memory, except for the instruction-cache line associated with
the reset vector.
■ Peripherals. Refer to the appropriate peripheral data sheet or
specification for reset conditions.
■ Custom instruction logic. Refer to the custom instruction
specification for reset conditions.
■ Nios II C-to-hardware (C2H) acceleration compiler logic. Refer to the
C2H compiler specification for reset conditions.
Break Exceptions
A break is a transfer of control away from a program’s normal flow of
execution for the purpose of debugging. Software debugging tools can
take control of the Nios II processor via the JTAG debug module. Only
debugging tools control the processor when executing in debug mode;
application and system code never execute in this mode.
Break processing is the means by which software debugging tools
implement debug and diagnostic features, such as breakpoints and
watchpoints. Break processing is a type of exception processing, but the
break mechanism is independent from general exception processing. A
break can occur during exception processing, enabling debug tools to
debug exception handlers.
The processor enters the break processing state under any of the
following conditions:
■ The processor executes the break instruction. This is often referred
to as a software break.
■ The JTAG debug module asserts a hardware break.
Processing a Break
A break causes the processor to take the following steps:
1. Stores the contents of the status register to bstatus
2. Clears the PIE bit of the status register, disabling external
processor interrupts