Specifications

3–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
Exception Processing
■ Instruction-related exceptions
Table 3–4 shows all possible Nios II exceptions in order of highest to
lowest priority. For each exception, an exception vector along with any
control register indications help determine the exception type.
The following sections describe each exception type in detail.
Reset Exceptions
When a processor reset signal is asserted, the Nios II processor performs
the following steps:
1. Clears the status register to 0x0
2. Invalidates the instruction-cache line associated with the reset
vector
3. Begins executing the reset handler, located at the reset vector
Clearing the status register disables hardware interrupts. Invalidating
the reset cache line guarantees that instruction fetches for reset code
comes from uncached memory.
Aside from the instruction-cache line associated with the reset vector, the
contents of the cache memories are indeterminate after reset. To ensure
cache coherency after reset, the reset handler located at the reset vector
must immediately initialize the instruction cache. Next, either the reset
handler or a subsequent routine should proceed to initialize the data
cache.
Table 3–4. Nios II Exceptions (In Decreasing Priority Order)
Exception Exception Type Exception Vector
Control Register
Indications
Reset Reset Reset none
Hardware Break Break Break none
CPU-only Reset Request Reset Reset none
Interrupt Interrupt General exception
EPIE of estatus is one
and
ipending non-zero
● Trap instruction
● Break instruction
● Unimplemented instruction
Instruction-related General exception
(except break
instruction is Break)
BAD of tlbmisc is one
or instruction decode