Specifications

Altera Corporation v
Nios II Processor Reference Handbook
Contents
Chapter 4. Instantiating the Nios II Processor in SOPC Builder
Introduction ............................................................................................................................................ 4–1
Core Nios II Page ................................................................................................................................... 4–2
Core Selection ................................................................................................................................... 4–3
Multiply and Divide Settings ......................................................................................................... 4–3
Reset Vector ....................................................................................................................................... 4–4
Exception Vector ............................................................................................................................... 4–4
Caches and Memory Interfaces Page .................................................................................................. 4–6
Instruction Master Settings ............................................................................................................. 4–7
Data Master Settings ........................................................................................................................ 4–8
Advanced Features Page ...................................................................................................................... 4–9
Reset Signals .................................................................................................................................... 4–10
JTAG Debug Module Page ................................................................................................................. 4–10
Debug Level Settings ..................................................................................................................... 4–12
Break Vector .................................................................................................................................... 4–13
Advanced Debug Settings ............................................................................................................. 4–14
Custom Instructions Page .................................................................................................................. 4–14
Interrupt Vector Custom Instruction ........................................................................................... 4–16
Floating Point Hardware Custom Instruction ........................................................................... 4–17
Endian Converter Custom Instruction ........................................................................................ 4–18
Bitswap Custom Instruction ......................................................................................................... 4–19
Referenced Documents ....................................................................................................................... 4–19
Document Revision History ............................................................................................................... 4–20
Section II. Appendices
Chapter 5. Nios II Core Implementation Details
Introduction ............................................................................................................................................ 5–1
Device Family Support ......................................................................................................................... 5–3
Nios II/f Core ......................................................................................................................................... 5–3
Overview ........................................................................................................................................... 5–4
Arithmetic Logic Unit ...................................................................................................................... 5–4
Memory Access ................................................................................................................................. 5–6
Tightly-Coupled Memory ............................................................................................................... 5–8
Execution Pipeline ............................................................................................................................ 5–9
Instruction Performance ................................................................................................................ 5–10
Exception Handling ....................................................................................................................... 5–11
JTAG Debug Module ..................................................................................................................... 5–12
Unsupported Features ................................................................................................................... 5–12
Nios II/s Core ...................................................................................................................................... 5–12
Overview ......................................................................................................................................... 5–12
Arithmetic Logic Unit .................................................................................................................... 5–13
Memory Access ............................................................................................................................... 5–14
Tightly-Coupled Memory ............................................................................................................. 5–15
Execution Pipeline .......................................................................................................................... 5–16