Specifications

Altera Corporation 3–5
October 2007 Nios II Processor Reference Handbook
Programming Model
The following sections define the modes and the transitions between
modes.
Normal Mode
In general, system and application code execute in normal mode. The
processor is in normal mode immediately after processor reset.
General-purpose registers bt (r25) and ba (r30) are reserved for
debugging and are not available in normal mode. Programs are not
prevented from storing values in these registers, but if they do, the debug
mode could overwrite the values. The bstatus control register is also
unavailable in normal mode.
Debug Mode
Software debugging tools use debug mode to implement features such as
breakpoints and watchpoints. System code and application code never
execute in debug mode. The processor enters debug mode only after the
break instruction or after the JTAG debug module forces a break via
hardware.
In debug mode all processor functions are available and unrestricted to
the software debugging tool. See “Break Exceptions” on page 3–7 for
further information.
Changing Modes
The processor starts in normal mode after reset. It enters debug mode in
response to a break instruction or as directed by software debugging
tools. Except by executing a break instruction, system code and
application code have no control over when the processor enters debug
mode. The processor always returns to its prior state when exiting from
debug mode. See “Break Exceptions” on page 3–7 for further information.
Exception
Processing
An exception is a transfer of control away from a program’s normal flow
of execution, caused by an event, either internal or external to the
processor, which requires immediate attention. Exception processing is
the act of responding to an exception, and then returning to the pre-
exception execution state.
Each of the Nios II exceptions falls into one of the following categories:
■ Reset exceptions
■ Break exceptions
■ Interrupt exceptions