Specifications

3–4 Altera Corporation
Nios II Processor Reference Handbook October 2007
Operating Modes
bstatus
The bstatus register holds a saved copy of the status register during
break exception processing. One bit is defined: BPIE. This is the saved
value of PIE, as defined in Table 3–3.
When a break occurs, the value of the status register is copied into
bstatus. Using bstatus, the debugger can restore the status register
to the value prior to the break. The bret instruction causes the processor
to copy bstatus back to status. See “Debug Mode” on page 3–5 for
more information.
ienable
The ienable register controls the handling of external hardware
interrupts. Each bit of the ienable register corresponds to one of the
interrupt inputs, irq0 through irq31. A value of one in bit n means that
the corresponding irqn interrupt is enabled; a bit value of zero means
that the corresponding interrupt is disabled. See “Exception Processing”
on page 3–5 for more information.
ipending
The value of the ipending register indicates the value of the interrupt
signals driven into the processor. A value of one in bit n means that the
corresponding irqn input is asserted. Writing a value to the ipending
register has no effect.
cpuid
The cpuid register holds a constant value that uniquely identifies each
processor in a multi-processor system. The cpuid value is determined at
system generation time and is guaranteed to be unique for each processor
in the system. Writing to the cpuid register has no effect.
Operating
Modes
The Nios II processor has two operating modes:
■ Normal mode
■ Debug mode