Specifications

Altera Corporation 3–1
October 2007
3. Programming Model
Introduction
This chapter describes the Nios
®
II programming model, covering
processor features at the assembly language level. Fully understanding
the contents of this chapter requires prior knowledge of computer
architecture, exception handling, and instruction sets. This chapter
assumes you have a detailed understanding of the aforementioned
concepts and focuses on how these concepts are specifically implemented
in the Nios II processor. Where possible, this chapter uses industry-
standard terminology.
The following features are discussed from the programmer’s perspective:
■ General-purpose registers, page 3–1
■ Control registers, page 3–2
■ Operating modes, page 3–4
■ Exception processing, page 3–5
■ Processor reset state, page 3–6
■ Hardware-assisted debug processing, page 3–7
■ Hardware interrupts, page 3–8
■ Memory and peripheral organization, page 3–14
■ Cache memory, page 3–14
■ Instruction set categories, page 3–15
■ Custom instructions, page 3–21
f High-level software development tools are not discussed here. See the
Nios II Software Developer’s Handbook for information about developing
software.
General-
Purpose
Registers
The Nios II architecture provides thirty-two 32-bit general-purpose
registers, r0 through r31, as shown in Table 3–1. Some registers have
names recognized by the assembler. The zero register (r0) always
returns the value zero, and writing to zero has no effect. The ra register
(r31) holds the return address used by procedure calls and is implicitly
NII51003-7.2.0