Specifications

Altera Corporation 2–19
October 2007 Nios II Processor Reference Handbook
Processor Architecture
Trace Frames
A “frame” is a unit of memory allocated for collecting trace data.
However, a frame is not an absolute measure of the trace depth.
To keep pace with the processor executing in real time, execution trace is
optimized to store only selected addresses, such as branches, calls, traps,
and interrupts. From these addresses, host-side debug software can later
reconstruct an exact instruction-by-instruction execution trace.
Furthermore, execution trace data is stored in a compressed format, such
that one frame represents more than one instruction. As a result of these
optimizations, the actual start and stop points for trace collection during
execution might vary slightly from the user-specified start and stop
points.
Data trace stores 100% of requested loads and stores to the trace buffer in
real time. When storing to the trace buffer, data trace frames have lower
priority than execution trace frames. Therefore, while data frames are
always stored in chronological order, execution and data trace are not
guaranteed to be exactly synchronized with each other.
Referenced
Documents
This chapter references the following documents:
■ Nios II Core Implementation Details chapter of the Nios II Processor
Reference Handbook
■ Instantiating the Nios II Processor in SOPC Builder chapter of the Nios II
Processor Reference Handbook
■ Nios II Custom Instruction User Guide
■ Instruction Set Reference chapter of the Nios II Processor Reference
Handbook
■ Programming Model chapter of the Nios II Processor Reference Handbook
■ Avalon Memory Mapped Interface Specification