Specifications

2–18 Altera Corporation
Nios II Processor Reference Handbook October 2007
JTAG Debug Module
Trace Capture
Trace capture refers to ability to record the instruction-by-instruction
execution of the processor as it executes code in real-time. The JTAG
debug module offers the following trace features:
■ Capture execution trace (instruction bus cycles).
■ Capture data trace (data bus cycles).
■ For each data bus cycle, capture address, data, or both.
■ Start and stop capturing trace in real time, based on triggers.
■ Manually start and stop trace under host control.
■ Optionally stop capturing trace when trace buffer is full, leaving the
processor executing.
■ Store trace data in on-chip memory buffer in the JTAG debug
module. (This memory is accessible only through the JTAG
connection.)
■ Store trace data to larger buffers in an off-chip debug probe.
Certain trace features require additional licensing or debug tools from
third-party debug providers. For example, an on-chip trace buffer is a
standard feature of the Nios II processor, but using an off-chip trace
buffer requires additional debug software and hardware provided by
First Silicon Solutions (FS2) or Lauterbach.
f For details, see www.fs2.com and www.lauterbach.com.
Execution vs. Data Trace
The JTAG debug module supports tracing the instruction bus (execution
trace), the data bus (data trace), or both simultaneously. Execution trace
records only the addresses of the instructions executed, enabling you to
analyze where in memory (i.e., in which functions) code executed. Data
trace records the data associated with each load and store operation on
the data bus.
The JTAG debug module can filter the data bus trace in real time to
capture the following:
■ Load addresses only
■ Store addresses only
■ Both load and store addresses
■ Load data only
■ Load address and data
■ Store address and data
■ Address and data for both loads and stores
■ Single sample of the data bus upon trigger event