Specifications

Altera Corporation 2–17
October 2007 Nios II Processor Reference Handbook
Processor Architecture
Armed Triggers
The JTAG debug module provides a two-level trigger capability, called
armed triggers. Armed triggers enable the JTAG debug module to trigger
on event B, only after event A. In this example, event A causes a trigger
action that enables the trigger for event B.
Triggering on Ranges of Values
The JTAG debug module can trigger on ranges of data or address values
on the data bus. This mechanism uses two hardware triggers together to
create a trigger condition that activates on a range of values within a
specified range.
Table 2–4. Trigger Conditions
Condition
Bus
(1)
Description
Specific address D, I Trigger when the bus accesses a specific address.
Specific data value D Trigger when a specific data value appears on the bus.
Read cycle D Trigger on a read bus cycle.
Write cycle D Trigger on a write bus cycle.
Armed D, I Trigger only after an armed trigger event. See “Armed Triggers” on page 2–17.
Range D Trigger on a range of address values, data values, or both. See “Triggering on
Ranges of Values” on page 2–17.
Notes:
(1) “I” indicates instruction bus, “D” indicates data bus.
Table 2–5. Trigger Actions
Action Description
Break Halt execution and transfer control to the JTAG debug module.
External trigger Assert a trigger signal output. This trigger output can be used, for example, to trigger an
external logic analyzer.
Trace on Turn on trace collection.
Trace off Turn off trace collection.
Trace sample (1)
Store one sample of the bus to trace buffer.
Arm Enable an armed trigger.
Notes:
(1) Only conditions on the data bus can trigger this action.