Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

2–16 Altera Corporation
Nios II Processor Reference Handbook October 2007
JTAG Debug Module
Download and Execute Software
Downloading software refers to the ability to download executable code
and data to the processor’s memory via the JTAG connection. After
downloading software to memory, the JTAG debug module can then exit
debug mode and transfer execution to the start of executable code.
Software Breakpoints
Software breakpoints provide the ability to set a breakpoint on
instructions residing in RAM. The software breakpoint mechanism writes
a break instruction into executable code stored in RAM. When the
processor executes the break instruction, control is transferred to the
JTAG debug module.
Hardware Breakpoints
Hardware breakpoints provide the ability to set a breakpoint on
instructions residing in nonvolatile memory, such as flash memory. The
hardware breakpoint mechanism continuously monitors the processor’s
current instruction address. If the instruction address matches the
hardware breakpoint address, the JTAG debug module takes control of
the processor.
Hardware breakpoints are implemented using the JTAG debug module’s
hardware trigger feature.
Hardware Triggers
Hardware triggers activate a debug action based on conditions on the
instruction or data bus during real-time program execution. Triggers can
do more than halt processor execution. For example, a trigger can be used
to enable trace data collection during real-time processor execution.
Table 2–4 lists all the conditions that can cause a trigger. Hardware trigger
conditions are based on either the instruction or data bus. Trigger
conditions on the same bus can be logically ANDed, enabling the JTAG
debug module to trigger, for example, only on write cycles to a specific
address.
When a trigger condition occurs during processor execution, the JTAG
debug module triggers an action, such as halting execution, or starting
trace capture. Table 2–5 lists the trigger actions supported by the Nios II
JTAG debug module.