Specifications

iv Altera Corporation
Nios II Processor Reference Handbook
Contents
Memory and I/O Organization ........................................................................................................... 2–8
Instruction and Data Buses ............................................................................................................. 2–9
Cache Memory ................................................................................................................................ 2–11
Tightly-Coupled Memory ............................................................................................................. 2–13
Address Map ................................................................................................................................... 2–14
JTAG Debug Module .......................................................................................................................... 2–15
JTAG Target Connection ............................................................................................................... 2–15
Download and Execute Software ................................................................................................. 2–16
Software Breakpoints ..................................................................................................................... 2–16
Hardware Breakpoints .................................................................................................................. 2–16
Hardware Triggers ......................................................................................................................... 2–16
Trace Capture .................................................................................................................................. 2–18
Referenced Documents ....................................................................................................................... 2–19
Document Revision History ............................................................................................................... 2–20
Chapter 3. Programming Model
Introduction ............................................................................................................................................ 3–1
General-Purpose Registers ................................................................................................................... 3–1
Control Registers ................................................................................................................................... 3–2
Operating Modes ................................................................................................................................... 3–4
Normal Mode .................................................................................................................................... 3–5
Debug Mode ...................................................................................................................................... 3–5
Changing Modes .............................................................................................................................. 3–5
Exception Processing ............................................................................................................................. 3–5
Reset Exceptions ............................................................................................................................... 3–6
Break Exceptions .............................................................................................................................. 3–7
Interrupt Exceptions ........................................................................................................................ 3–8
Instruction-Related Exceptions .................................................................................................... 3–10
Processing Interrupt and Instruction-Related Exceptions ....................................................... 3–11
Determining the Cause of Interrupt and Instruction-Related Exceptions ............................. 3–12
Returning From Interrupt and Instruction-Related Exceptions .............................................. 3–13
Memory and Peripheral Access ......................................................................................................... 3–14
Cache Memory ................................................................................................................................ 3–14
Instruction Set Categories ................................................................................................................... 3–15
Data Transfer Instructions ............................................................................................................ 3–15
Arithmetic and Logical Instructions ............................................................................................ 3–16
Move Instructions ........................................................................................................................... 3–17
Comparison Instructions ............................................................................................................... 3–17
Shift and Rotate Instructions ........................................................................................................ 3–18
Program Control Instructions ....................................................................................................... 3–19
Other Control Instructions ............................................................................................................ 3–20
Custom Instructions ....................................................................................................................... 3–21
No-Operation Instruction ............................................................................................................. 3–21
Potential Unimplemented Instructions ....................................................................................... 3–21
Referenced Documents ....................................................................................................................... 3–21
Document Revision History ............................................................................................................... 3–22