Specifications

Altera Corporation 2–15
October 2007 Nios II Processor Reference Handbook
Processor Architecture
JTAG Debug
Module
The Nios II architecture supports a JTAG debug module that provides on-
chip emulation features to control the processor remotely from a host PC.
PC-based software debugging tools communicate with the JTAG debug
module and provide facilities, such as:
■ Downloading programs to memory
■ Starting and stopping execution
■ Setting breakpoints and watchpoints
■ Analyzing registers and memory
■ Collecting real-time execution trace data
The debug module connects to the JTAG circuitry in an Altera
®
FPGA.
External debugging probes can then access the processor via the standard
JTAG interface on the FPGA. On the processor side, the debug module
connects to signals inside the processor core. The debug module has non-
maskable control over the processor, and does not require a software stub
linked into the application under test. All system resources visible to the
processor in supervisor mode are available to the debug module. For
trace data collection, the debug module stores trace data in memory
either on-chip or in the debug probe.
The debug module gains control of the processor either by asserting a
hardware break signal, or by writing a break instruction into program
memory to be executed. In both cases, the processor transfers control to a
routine located at the break address. The break address is specified at
system generation time.
Soft-core processors such as the Nios II processor offer unique debug
capabilities beyond the features of traditional, fixed processors. The soft-
core nature of the Nios II processor allows you to debug a system in
development using a full-featured debug core, and later remove the
debug features to conserve logic resources. For the release version of a
product, the JTAG debug module functionality can be reduced, or
removed altogether.
The following sections describe the capabilities of the Nios II JTAG debug
module hardware. The usage of all hardware features is dependent on
host software, such as the Nios II IDE, which manages the connection to
the target processor and controls the debug process.
JTAG Target Connection
The JTAG target connection refers to the ability to connect to the
processor through the standard JTAG pins on the Altera FPGA. This
provides the basic capabilities to start and stop the processor, and
examine/edit registers and memory. The JTAG target connection is also
the minimum requirement for the Nios II IDE flash programmer.