Specifications

2–12 Altera Corporation
Nios II Processor Reference Handbook October 2007
Memory and I/O Organization
core. The cache memories can improve the average memory access time
for Nios II processor systems that use slow off-chip memory such as
SDRAM for program and data storage.
The instruction and data caches are enabled perpetually at run-time, but
methods are provided for software to bypass the data cache so that
peripheral accesses do not return cached data. Cache management and
cache coherency are handled by software. The Nios II instruction set
provides instructions for cache management.
Configurable Cache Memory Options
The cache memories are optional. The need for higher memory
performance (and by association, the need for cache memory) is
application dependent. Many applications require the smallest possible
processor core, and can trade-off performance for size.
A Nios II processor core might include one, both, or neither of the cache
memories. Furthermore, for cores that provide data and/or instruction
cache, the sizes of the cache memories are user-configurable. The
inclusion of cache memory does not affect the functionality of programs,
but it does affect the speed at which the processor fetches instructions and
reads/writes data.
Effective Use of Cache Memory
The effectiveness of cache memory to improve performance is based on
the following premises:
■ Regular memory is located off-chip, and access time is long
compared to on-chip memory
■ The largest, performance-critical instruction loop is smaller than the
instruction cache
■ The largest block of performance-critical data is smaller than the data
cache
Optimal cache configuration is application specific, although you can
make decisions that are effective across a range of applications. For
example, if a Nios II processor system includes only fast, on-chip memory
(i.e., it never accesses slow, off-chip memory), an instruction or data cache
is unlikely to offer any performance gain. As another example, if the
critical loop of a program is 2 KBytes, but the size of the instruction cache
is 1 KByte, an instruction cache does not improve execution speed. In fact,
an instruction cache may degrade performance in this situation.