Specifications

Altera Corporation 2–11
October 2007 Nios II Processor Reference Handbook
Processor Architecture
Data Master Port
The Nios II data bus is implemented as a 32-bit Avalon-MM master port.
The data master port performs two functions:
■ Read data from memory or a peripheral when the processor executes
a load instruction
■ Write data to memory or a peripheral when the processor executes a
store instruction
Byte-enable signals on the master port specify which of the four byte-
lane(s) to write during store operations. When the Nios II core is
configured with a data cache line size greater than four bytes, the data
master port supports pipelined Avalon-MM transfers. When the data
cache line size is only four bytes, any memory pipeline latency is
perceived by the data master port as wait states. Load and store
operations can complete in a single clock-cycle when the data master port
is connected to zero-wait-state memory.
The Nios II architecture supports on-chip cache memory for improving
average data transfer performance when accessing slower memory. See
“Cache Memory” for details. The Nios II architecture supports tightly-
coupled memory, which provides guaranteed low-latency access to on-
chip memory. Refer to “Tightly-Coupled Memory” on page 2–13 for
details.
Shared Memory for Instructions and Data
Usually the instruction and data master ports share a single memory that
contains both instructions and data. While the processor core has separate
instruction and data buses, the overall Nios II processor system might
present a single, shared instruction/data bus to the outside world. The
outside view of the Nios II processor system depends on the memory and
peripherals in the system and the structure of the system interconnect
fabric.
The data and instruction master ports never cause a gridlock condition in
which one port starves the other. For highest performance, assign the data
master port higher arbitration priority on any memory that is shared by
both instruction and data master ports.
Cache Memory
The Nios II architecture supports cache memories on both the instruction
master port (instruction cache) and the data master port (data cache).
Cache memory resides on-chip as an integral part of the Nios II processor