Specifications

2–10 Altera Corporation
Nios II Processor Reference Handbook October 2007
Memory and I/O Organization
Memory and Peripheral Access
The Nios II architecture provides memory-mapped I/O access. Both data
memory and peripherals are mapped into the address space of the data
master port. The Nios II architecture is little endian. Words and halfwords
are stored in memory with the more-significant bytes at higher addresses.
The Nios II architecture does not specify anything about the existence of
memory and peripherals; the quantity, type, and connection of memory
and peripherals are system-dependent. Typically, Nios II processor
systems contain a mix of fast on-chip memory and slower off-chip
memory. Peripherals typically reside on-chip, although interfaces to off-
chip peripherals also exist.
Instruction Master Port
The Nios II instruction bus is implemented as a 32-bit Avalon-MM master
port. The instruction master port performs a single function: it fetches
instructions to be executed by the processor. The instruction master port
does not perform any write operations.
The instruction master port is a pipelined Avalon-MM master port.
Support for pipelined Avalon-MM transfers minimizes the impact of
synchronous memory with pipeline latency and increases the overall
f
MAX
of the system. The instruction master port can issue successive read
requests before data has returned from prior requests. The Nios II
processor can prefetch sequential instructions and perform branch
prediction to keep the instruction pipe as active as possible.
The instruction master port always retrieves 32 bits of data. The
instruction master port relies on dynamic bus-sizing logic contained in
the system interconnect fabric. By virtue of dynamic bus sizing, every
instruction fetch returns a full instruction word, regardless of the width
of the target memory. Consequently, programs do not need to be aware of
the widths of memory in the Nios II processor system.
The Nios II architecture supports on-chip cache memory for improving
average instruction fetch performance when accessing slower memory.
See “Cache Memory” on page 2–11 for details. The Nios II architecture
supports tightly-coupled memory, which provides guaranteed low-
latency access to on-chip memory. See “Tightly-Coupled Memory” on
page 2–13 for details.