Specifications

Altera Corporation 2–9
October 2007 Nios II Processor Reference Handbook
Processor Architecture
f For details that affect programming issues, see the Programming Model
chapter of the Nios II Processor Reference Handbook.
Figure 2–2 shows a diagram of the memory and I/O organization for a
Nios II processor core.
Figure 2–2. Nios II Memory and I/O Organization
Instruction and Data Buses
The Nios II architecture supports separate instruction and data buses,
classifying it as a Harvard architecture. Both the instruction and data
buses are implemented as Avalon-MM master ports that adhere to the
Avalon-MM interface specification. The data master port connects to both
memory and peripheral components, while the instruction master port
connects only to memory components.
f Refer to the Avalon Memory Mapped Interface Specification for details of the
Avalon-MM interface.
S
Memory
S
Slave
Peripheral
Avalon Master Port
Avalon Slave Port
M
S
M
M
Tightly Coupled
Instruction
Memory N
Tightly Coupled
Data
Memory 1
Instruction
Cache
Data
Cache
Nios II Processor Core
Avalon Switch
Fabric
Program
Counter
General
Purpose
Register
File
Instruction
Bus
Selector
Logic
Tightly Coupled
Data
Memory N
Tightly Coupled
Instruction
Memory 1
Data
Bus
Selector
Logic