Specifications

2–8 Altera Corporation
Nios II Processor Reference Handbook October 2007
Memory and I/O Organization
f For an explanation of the instruction reference format, see the Instruction
Set Reference chapter of the Nios II Processor Reference Handbook.
Memory and I/O
Organization
This section explains hardware implementation details of the Nios II
memory and I/O organization. The discussion covers both general
concepts true of all Nios II processor systems, as well as features that
might change from system to system.
The flexible nature of the Nios II memory and I/O organization are the
most notable difference between Nios II processor systems and
traditional microcontrollers. Because Nios II processor systems are
configurable, the memories and peripherals vary from system to system.
As a result, the memory and I/O organization varies from system to
system.
A Nios II core uses one or more of the following to provide memory and
I/O access:
■ Instruction master port - An Avalon-MM master port that connects
to instruction memory via system interconnect fabric
■ Instruction cache - Fast cache memory internal to the Nios II core
■ Data master port - An Avalon-MM master port that connects to data
memory and peripherals via system interconnect fabric
■ Data cache - Fast cache memory internal to the Nios II core
■ Tightly-coupled instruction or data memory port - Interface to fast
on-chip memory outside the Nios II core
The Nios II architecture hides the hardware details from the programmer,
so programmers can develop Nios II applications without specific
knowledge of the hardware implementation.
Description: The interrupt vector custom instruction accelerates interrupt vector dispatch. This
custom instruction identifies the highest priority interrupt, generates the vector table
offset, and stores this offset to rC. The instruction generates a negative offset if there
is no hardware interrupt (that is, the exception is caused by a software condition, such
as a trap).
Usage: The interrupt vector custom instruction is used exclusively by the exception handler.
Instruction Type: R
Instruction Fields: C = Register index of operand rC
N = Value of ALT_CI_EXCEPTION_VECTOR_N
313029282726252423222120191817161514131211109876543210
0 0 C 001
N
0x32