Specifications

Altera Corporation 2–7
October 2007 Nios II Processor Reference Handbook
Processor Architecture
The software can enable and disable any interrupt source individually
through the ienable control register, which contains an interrupt-enable
bit for each of the IRQ inputs. Software can enable and disable interrupts
globally using the PIE bit of the status control register. A hardware
interrupt is generated if and only if all three of these conditions are true:
■ The PIE bit of the status register is 1
■ An interrupt-request input, irq<n>, is asserted
■ The corresponding bit n of the ienable register is 1
Interrupt Vector Custom Instruction
The Nios II processor core offers an interrupt vector custom instruction
which accelerates interrupt vector dispatch. Include this custom
instruction to reduce your program’s interrupt latency.
The interrupt vector custom instruction is based on a priority encoder
with one input for each interrupt connected to the Nios II processor. The
cost of the interrupt vector custom instruction depends on the number of
interrupts connected to the Nios II processor. The worst case is a system
with 32 interrupts. In this case, the interrupt vector custom instruction
consumes about 50 logic elements (LEs).
If you have a large number of interrupts connected, adding the interrupt
vector custom instruction to your system might lower f
MAX
.
f For guidance in adding the interrupt vector custom instruction to the
Nios II processor, refer to the Instantiating the Nios II Processor in SOPC
Builder chapter of the Nios II Processor Reference Handbook.
Table 2–3 details the implementation of the interrupt vector custom
instruction.
Table 2–3. Interrupt Vector Custom Instruction
ALT_CI_EXCEPTION_VECTOR_N
Operation:
if (
ipending == 0) | (estatus.PIE == 0)
then rC
←
negative value
else rC
←
8 × bit # of the least-significant 1 bit of the
ipending register (ctl4)
Assembler Syntax:
custom ALT_CI_EXCEPTION_VECTOR_N, rC, r0, r0
Example:
custom ALT_CI_EXCEPTION_VECTOR_N, et, r0, r0
blt et, r0, not_irq