Specifications

2–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
Reset Signals
1 The floating point custom instructions can be added to any
Nios II processor core. The Nios II software development tools
recognize C code that can take advantage of the floating point
instructions when they are present in the processor core.
Reset Signals
The Nios II processor core supports two reset signals.
■ reset - This a global hardware reset signal that forces the processor
core to reset immediately.
■ cpu_resetrequest - This is an local reset signal that causes the
processor to reset without affecting other components in the Nios II
system. The processor finishes executing any instructions in the
pipeline, and then enters the reset state. This process can take several
clock cycles. The processor core asserts the cpu_resettaken signal
for 1 cycle when the reset is complete and then periodically if
cpu_resetrequest remains asserted. The processor remains in reset
for as long as cpu_resetrequest is asserted.
While the processor is in reset, it periodically reads from the reset
address. It discards the result of the read, and remains in reset.
The processor does not respond to cpu_resetrequest when the
processor is under the control of the JTAG debug module, that is,
when the processor is paused. The processor responds to the
cpu_resetrequest signal if the signal is asserted when the JTAG
debug module relinquishes control, both momentarily during each
single step as well as when you resume execution.
Exception and
Interrupt
Controller
Exception Controller
The Nios II architecture provides a simple, non-vectored exception
controller to handle all exception types. All exceptions, including
hardware interrupts, cause the processor to transfer execution to a single
exception address. The exception handler at this address determines the
cause of the exception and dispatches an appropriate exception routine.
The exception address is specified at system generation time.
Integral Interrupt Controller
The Nios II architecture supports 32 external hardware interrupts. The
processor core has 32 level-sensitive interrupt request (IRQ) inputs, irq0
through irq31, providing a unique input for each interrupt source. IRQ
priority is determined by software. The architecture supports nested
interrupts.