Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

Altera Corporation iii
Contents
Chapter Revision Dates ........................................................................... ix
About This Handbook .............................................................................. xi
Introduction ............................................................................................................................................... xi
Prerequisites ..................................................................................................................................... 1–xi
How to Find Further Information ........................................................................................................ xii
How to Contact Altera ........................................................................................................................... xii
Typographical Conventions ................................................................................................................. xiii
Section I. Nios II Processor
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Nios II Processor System Basics .......................................................................................................... 1–1
Getting Started with the Nios II Processor ........................................................................................ 1–2
Customizing Nios II Processor Designs ............................................................................................. 1–3
Configurable Soft-Core Processor Concepts ...................................................................................... 1–4
Configurable Soft-Core Processor .................................................................................................. 1–4
Flexible Peripheral Set and Address Map .................................................................................... 1–5
Custom Instructions ......................................................................................................................... 1–5
Automated System Generation ...................................................................................................... 1–6
OpenCore Plus Evaluation ................................................................................................................... 1–6
Referenced Documents ......................................................................................................................... 1–7
Document Revision History ................................................................................................................. 1–7
Chapter 2. Processor Architecture
Introduction ............................................................................................................................................ 2–1
Processor Implementation .................................................................................................................... 2–2
Register File ............................................................................................................................................ 2–3
Arithmetic Logic Unit ........................................................................................................................... 2–4
Unimplemented Instructions .......................................................................................................... 2–4
Custom Instructions ......................................................................................................................... 2–4
Floating Point Instructions .............................................................................................................. 2–5
Reset Signals ........................................................................................................................................... 2–6
Exception and Interrupt Controller .................................................................................................... 2–6
Exception Controller ........................................................................................................................ 2–6
Integral Interrupt Controller ........................................................................................................... 2–6
Interrupt Vector Custom Instruction ............................................................................................. 2–7