Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

2–4 Altera Corporation
Nios II Processor Reference Handbook October 2007
Arithmetic Logic Unit
Arithmetic Logic
Unit
The Nios II arithmetic logic unit (ALU) operates on data stored in
general-purpose registers. ALU operations take one or two inputs from
registers, and store a result back in a register. The ALU supports the data
operations shown in Table 2–1:
To implement any other operation, software computes the result by
performing a combination of the fundamental operations in Table 2–1.
Unimplemented Instructions
Some Nios II processor core implementations do not provide hardware to
perform multiplication or division operations. The following instructions
are not present in all Nios II core implementations: mul, muli, mulxss,
mulxsu, mulxuu, div, divu. In such a core, these are known as
unimplemented instructions. All other instructions are implemented in
hardware.
The processor generates an exception whenever it issues an
unimplemented instruction, and the exception handler calls a routine that
emulates the operation in software. Therefore, unimplemented
instructions do not affect the programmer’s view of the processor.
Custom Instructions
The Nios II architecture supports user-defined custom instructions. The
Nios II ALU connects directly to custom instruction logic, enabling you to
implement in hardware operations that are accessed and used exactly like
native instructions.
f For further information see the Nios II Custom Instruction User Guide.
Table 2–1. Operations Supported by the Nios II ALU
Category Details
Arithmetic The ALU supports addition, subtraction, multiplication, and division on signed and unsigned
operands.
Relational The ALU supports the equal, not-equal, greater-than-or-equal, and less-than relational
operations ( ==, != >=, < ) on signed and unsigned operands.
Logical The ALU supports AND, OR, NOR, and XOR logical operations.
Shift and Rotate The ALU supports shift and rotate operations, and can shift/rotate data by 0 to 31 bit-positions
per instruction. The ALU supports arithmetic shift right and logical shift right/left. The ALU
supports rotate left/right.