Specifications

Altera Corporation 2–3
October 2007 Nios II Processor Reference Handbook
Processor Architecture
instruction set, not a particular hardware implementation. A functional
unit can be implemented in hardware, emulated in software, or omitted
entirely.
A Nios II implementation is a set of design choices embodied by a
particular Nios II processor core. All implementations support the
instruction set defined in the Nios II Processor Reference Handbook. Each
implementation achieves specific objectives, such as smaller core size or
higher performance. This allows the Nios II architecture to adapt to the
needs of different target applications.
Implementation variables generally fit one of three trade-off patterns:
more-or-less of a feature; inclusion-or-exclusion of a feature; hardware
implementation or software emulation of a feature. An example of each
trade-off follows:
■ More or less of a feature—For example, to fine-tune performance, you
can increase or decrease the amount of instruction cache memory. A
larger cache increases execution speed of large programs, while a
smaller cache conserves on-chip memory resources.
■ Inclusion or exclusion of a feature—For example, to reduce cost, you can
choose to omit the JTAG debug module. This decision conserves on-
chip logic and memory resources, but it eliminates the ability to use
a software debugger to debug applications.
■ Hardware implementation or software emulation—For example, in
control applications that rarely perform complex arithmetic, you can
choose for the division instruction to be emulated in software.
Removing the divide hardware conserves on-chip resources but
increases the execution time of division operations.
f For details of which Nios II cores supports what features, refer to the
Nios II Core Implementation Details chapter of the Nios II Processor
Reference Handbook. For complete details of user-selectable parameters for
the Nios II processor, refer to the Instantiating the Nios II Processor in
SOPC Builder chapter of the Nios II Processor Reference Handbook.
Register File
The Nios II architecture supports a flat register file, consisting of thirty
two 32-bit general-purpose integer registers, and up to thirty two 32-bit
control registers. The architecture supports supervisor and user modes
that allow system code to protect the control registers from errant
applications.
The Nios II architecture allows for the future addition of floating point
registers.