Specifications

2–2 Altera Corporation
Nios II Processor Reference Handbook October 2007
Processor Implementation
Figure 2–1. Nios II Processor Core Block Diagram
The Nios II architecture defines the following user-visible functional
units:
■ Register file
■ Arithmetic logic unit
■ Interface to custom instruction logic
■ Exception controller
■ Interrupt controller
■ Instruction bus
■ Data bus
■ Instruction and data cache memories
■ Tightly-coupled memory interfaces for instructions and data
■ JTAG debug module
The following sections discuss hardware implementation details related
to each functional unit.
Processor
Implementation
The functional units of the Nios II architecture form the foundation for
the Nios II instruction set. However, this does not indicate that any unit
is implemented in hardware. The Nios II architecture describes an
Exception
Controller
Interrupt
Controller
Arithmetic
Logic Unit
General
Purpose
Registers
r0 to r31
Control
Registers
ctl0 to ctl5
Nios II Processor Core
reset
clock
JTAG
interface
to software
debugger
Custom
I/O
Signals
irq[31..0]
JTAG
Debug Module
Program
Controller
&
Address
Generation
Custom
Instruction
Logic
Data Bus
Tightly Coupled
Data Memory
Tightly Coupled
Data Memory
Data
Cache
Instruction
Cache
Instruction Bus
Tightly Coupled
Instruction Memory
Tightly Coupled
Instruction Memory
cpu_resetrequest
cpu_resettaken