Specifications

Altera Corporation 2–1
October 2007
2. Processor Architecture
Introduction
This chapter describes the hardware structure of the Nios
®
II processor,
including a discussion of all the functional units of the Nios II
architecture and the fundamentals of the Nios II processor hardware
implementation. This chapter contains the following sections:
■ “Processor Implementation” on page 2–2
■ “Register File” on page 2–3
■ “Arithmetic Logic Unit” on page 2–4
■ “Reset Signals” on page 2–6
■ “Exception and Interrupt Controller” on page 2–6
■ “Memory and I/O Organization” on page 2–8
■ “JTAG Debug Module” on page 2–15
The Nios II architecture describes an instruction set architecture (ISA). The
ISA in turn necessitates a set of functional units that implement the
instructions. A Nios II processor core is a hardware design that implements
the Nios II instruction set and supports the functional units described in
this document. The processor core does not include peripherals or the
connection logic to the outside world. It includes only the circuits
required to implement the Nios II architecture.
Figure 2–1 shows a block diagram of the Nios II processor core.
NII51002-7.2.0