Specifications

Altera Corporation 8–99
October 2007 Nios II Processor Reference Handbook
trap
trap
trap
Operation:
estatus
←
status
PIE
←
0
U
←
0
ea
←
PC + 4
PC
←
exception handler address
Assembler Syntax:
trap
Example:
trap
Description:
Saves the address of the next instruction in register
ea, saves the contents of the
status register in estatus, disables interrupts, and transfers execution to the
exception handler. The address of the exception handler is specified at system
generation time.
Usage:
To return from the exception handler, execute an
eret instruction.
Instruction Type: R
Instruction Fields: None
313029282726252423222120191817161514131211109876543210
0 0 0x1d 0x2d 0 0x3a