Specifications

Altera Corporation 8–95
October 2007 Nios II Processor Reference Handbook
stw / stwio
stw / stwio
store word to memory or I/O peripheral
Operation:
Mem32[rA + σ (IMM16)]
←
rB
Assembler Syntax:
stw rB, byte_offset(rA)
stwio rB, byte_offset(rA)
Example:
stw r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Stores rB to the memory location specified by the
effective byte address. The effective byte address must be word aligned. If the byte
address is not a multiple of 4, the operation is undefined.
Usage: In processors with a data cache, this instruction may not generate an Avalon-MM data
transfer immediately. Use the
stwio instruction for peripheral I/O. In processors with
a data cache,
stwio bypasses the cache and is guaranteed to generate an
Avalon-MM bus cycle. In processors without a data cache,
stwio acts like stw.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x15
Instruction format for
stw
313029282726252423222120191817161514131211109876543210
A B IMM16 0x35
Instruction format for
stwio