Specifications

8–94 Altera Corporation
Nios II Processor Reference Handbook October 2007
sth / sthio
sth / sthio
store halfword to memory or I/O peripheral
Operation:
Mem16[rA + σ (IMM16)]
←
rB
15..0
Assembler Syntax:
sth rB, byte_offset(rA)
sthio rB, byte_offset(rA)
Example:
sth r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Stores the low halfword of rB to the memory location
specified by the effective byte address. The effective byte address must be halfword
aligned. If the byte address is not a multiple of 2, the operation is undefined.
Usage: In processors with a data cache, this instruction may not generate an Avalon-MM data
transfer immediately. Use the sthio instruction for peripheral I/O. In processors with a
data cache,
sthio bypasses the cache and is guaranteed to generate an Avalon-MM
data transfer. In processors without a data cache,
sthio acts like sth.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x0d
Instruction format for
sth
313029282726252423222120191817161514131211109876543210
A B IMM16 0x2d
Instruction format for
sthio