Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

1–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
OpenCore Plus Evaluation
Because the processor is implemented on reprogrammable Altera FPGAs,
software and hardware engineers can work together to iteratively
optimize the hardware and test the results of software running on
hardware.
From the software perspective, custom instructions appear as machine-
generated assembly macros or C functions, so programmers do not need
to know assembly in order to use custom instructions.
Automated System Generation
Altera’s SOPC Builder design tool fully automates the process of
configuring processor features and generating a hardware design that
you program into an FPGA. The SOPC Builder graphical user interface
(GUI) enables you to configure Nios II processor systems with any
number of peripherals and memory interfaces. You can create entire
processor systems without performing any schematic or hardware
description-language (HDL) design entry. SOPC Builder can also import
HDL design files, providing an easy mechanism to integrate custom logic
into a Nios II processor system.
After system generation, you can download the design onto a board, and
debug software executing on the board. To the software developer, the
processor architecture of the design is set. Software development
proceeds in the same manner as for traditional, non-configurable
processors.
OpenCore Plus
Evaluation
You can evaluate the Nios II processor without a license. With Altera's
free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a Nios II processor within your system
■ Verify the functionality of your design, as well as evaluate its size
and speed quickly and easily
■ Generate time-limited device programming files for designs that
include Nios II processors
■ Program a device and verify your design in hardware
You only need to purchase a license for the Nios II processor when you
are completely satisfied with its functionality and performance, and want
to take your design to production.
For more information on OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.