Specifications

Altera Corporation 1–5
October 2007 Nios II Processor Reference Handbook
Introduction
Flexible Peripheral Set and Address Map
A flexible peripheral set is one of the most notable differences between
Nios II processor systems and fixed microcontrollers. Because of the soft-
core nature of the Nios II processor, you can easily build made-to-order
Nios II processor systems with the exact peripheral set required for the
target applications.
A corollary of flexible peripherals is a flexible address map. Altera
provides software constructs to access memory and peripherals
generically, independently of address location. Therefore, the flexible
peripheral set and address map does not affect application developers.
There are two broad classes of peripherals: standard peripherals and
custom peripherals.
Standard Peripherals
Altera provides a set of peripherals commonly used in microcontrollers,
such as timers, serial communication interfaces, general-purpose I/O,
SDRAM controllers, and other memory interfaces. The list of available
peripherals continues to grow as Altera and third-party vendors release
new soft peripheral cores.
Custom Peripherals
You can also create custom peripherals and integrate them into Nios II
processor systems. For performance-critical systems that spend most
CPU cycles executing a specific section of code, it is a common technique
to create a custom peripheral that implements the same function in
hardware. This approach offers a double performance benefit: the
hardware implementation is faster than software; and the processor is
free to perform other functions in parallel while the custom peripheral
operates on data.
Custom Instructions
Like custom peripherals, custom instructions allow you to increase
system performance by augmenting the processor with custom
hardware. The soft-core nature of the Nios II processor enables you to
integrate custom logic into the arithmetic logic unit (ALU). Similar to
native Nios II instructions, custom instruction logic can take values from
up to two source registers and optionally write back a result to a
destination register.